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基于嵌入式結構半導體芯片信息測試系統平臺設計
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Design of information testing system platform for semiconductor chip based on embedded structure
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    摘要:

    為解決因半導體芯片信息平均壓縮比較大而導致的信息測試時(shí)間過(guò)長(cháng)的問(wèn)題,設計基于嵌入式結構半導體芯片信息測試系統平臺。根據嵌入式終端體系布局形式,建立LeNet網(wǎng)絡(luò )模型,再以此為基礎,完善SMTExecutor結構的執行流程,實(shí)現信息測試系統平臺的工具集模塊設計。分別定義Deflate機制、LZ4機制,聯(lián)合數據信息參量,規范系統平臺同步化線(xiàn)程的執行模式,實(shí)現對半導體芯片信息的處理。按照嵌入式結構定義標準,生成配置文件,通過(guò)導入關(guān)鍵信息的方式,規劃量化測試條件,從而對命令詞進(jìn)行識別,實(shí)現對測試系統功能的優(yōu)化,聯(lián)合工具集模塊,完成基于嵌入式結構半導體芯片信息測試系統平臺的設計。實(shí)驗結果表明,上述系統平臺的應用,可以在數據導入過(guò)程中解決半導體芯片信息平均壓縮比過(guò)大的問(wèn)題,能夠大幅縮短信息測試時(shí)間,符合實(shí)際應用需求。

    Abstract:

    In the process of data import, in order to solve the problem that the information test time is too long due to the large average compression ratio of semiconductor chip information, a semiconductor chip information test system platform based on embedded structure is designed. According to the layout of the embedded terminal system, the LeNet network model is established. On this basis, the execution process of the SMTExecutor structure is improved, and the tool set module design of the information test system platform is realized. Define Deflate mechanism and LZ4 mechanism respectively, combine data information parameters, standardize the execution mode of system platform synchronization thread, and realize the processing of semiconductor chip information. According to the embedded structure definition standard, the configuration file is generated, and the quantitative test conditions are planned by importing the key information, so as to identify the command words, realize the optimization of the test system function, and complete the design of the embedded structure semiconductor chip information test system platform by combining the tool set module. The experimental results show that the application of the above system platform can solve the problem that the average compression ratio of semiconductor chip information is too large in the process of data import, and can greatly shorten the information test time, which meets the actual application requirements.

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常宜龍.基于嵌入式結構半導體芯片信息測試系統平臺設計計算機測量與控制[J].,2023,31(11):131-136.

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  • 收稿日期:2023-04-27
  • 最后修改日期:2023-05-31
  • 錄用日期:2023-05-31
  • 在線(xiàn)發(fā)布日期: 2023-11-23
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