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In order to realize the stable and rapid recognition of high-speed dynamic images, and transmit the recognized target images to the host computer, using the optimized background difference principle, a high-speed dynamic target recognition algorithm that can be calculated in parallel is designed and verified. FPGA as the main control chip realizes the efficient collection and real-time transmission of effective images. First, the system adopts pipeline processing to realize real-time data collection, and then uses ping-pong operation to realize the target recognition algorithm. Through paging operation on DDR3, the recognized dynamic target image is cached, and finally the USB3.0 chip is used to realize the upper computer. Real-time data transmission with FPGA. Experimental results show that the designed high-speed recognition algorithm for dynamic targets can effectively identify 6mm BB bullets, Capture rate up to 99% and the system can realize real-time transmission of dynamic target data.