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There are many internal resources in Field Program Gate Array (FPGA), among which the failure probability of interconnect resources is much higher than that of other on-chip resources. However, in many researches on interconnect testing, the generated test configurations are hardly able to cover the feedback-bridging faults, so it was rare to achieve 100% coverage of interconnection fault list. Therefore, the feedback bridge fault model is optimized by constraining the bridge faults within a single look-up table (LUT) and using single-term functions, so as to fundamentally solve the problem. Then, the corresponding constraints are set for the optimized feedback bridge faults, and the test configurations meeting the constraints are generated using the Boolean Satisfiability theory (SAT). Finally, the test configuration generation experiment of the ISCAS"89 benchmark circuit is carried out, and the experimental results show that the generated test vectors not only solve the coverage problem of feedback-bridging faults, but also achieve 100% coverage of the fault list with the minimum configuration times.