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FPGA verification has attracted much attention as an important means of FPGA product function and reliability. Verification of interface timing is usually done by post-layout simulation, but simulation after layout and routing takes a lot of time. This paper introduces a method of timing verification of SRAM interface based on feedback constraint, which links the input and output of FPGA, the verification results show that compared with dynamic simulation, this static timing verification method can locate the problems in timing design of FPGA interface earlier, faster and more accurately. It shortens the verification time and improves the verification efficiency and coverage.