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Aiming at the problem that the early control module of the remote sensing system memory has low control efficiency, the design of the data memory control module of the telemetry system based on FPGA is proposed. The module structure and functions are designed according to the overall design of the module. The module structure is composed of an auto test interface module, a low-speed read/write control module, and a high-speed stream read/write control module. The SATA2.0 interface is used as a storage medium design controller to construct different frames for data transfer conversion. The steady-state trigger interface circuit is designed to achieve the purpose of high-speed stream read/write control triggering. According to the main software flow, inserting registers in the combinatorial logic delays the logic and implements FPGA timing control. The time-sharing operation method is used to control the read/write mode of the controller in the command layer, so as to realize the control and transmission of the transmission layer completion frame. It can be seen from the experimental results that the highest control efficiency of the module is superior to the traditional module, which provides support for efficient data storage.