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With the expansion of FPGA design scale,STA can relieve the stess of Timing Simulation,shorten project cycle.The common STA is more FF_Based STA,but after synthesis,unexpected Latch can be generated.While the calculating algorithms of Latch_Based STA and FF_Based STA is different,for the purpose of reaching 100% coverage rate of SAT path,it is necessary for the Independent Verification Authority to do some research on Latch_Based STA .The conception of “Time Borrowed”,”Time Given” and the feature of Latch slack time was explained,its function graphic was abstracted. Two separate example was given by Prime Time( a tool of Computer model simulation)