国产欧美精品一区二区,中文字幕专区在线亚洲,国产精品美女网站在线观看,艾秋果冻传媒2021精品,在线免费一区二区,久久久久久青草大香综合精品,日韩美aaa特级毛片,欧美成人精品午夜免费影视

This paper proposed a method which employ FPGA to design PLC data output control IP core.By the control of internal timing pulse, the controller will accomplish the informatiom's addressing and read/write operations in storage unit with Y numbered address independently while the controller carrying out the output information command.This paper discusses the circuit composition and basic principle of the IP core.Using Verilog HDL language to implement the construction and the function of the hardware circuit.The test result shows that:while the PLC user program is running,the controller can read or write the data information according to the command independently,making the execution of the output data information command and other system function module in parallel operation to improve the speed of PLC instruction execution sequence.